Delta-Sigma ADC

For most kinds of ADCs : data rate equals sampling rate ,each input sample converts to one output code.
Delta-sigma ADC : acquires many input samples to produce one output code. 
Which implies Delta-sigma sampling algorithm lengthens the acquisition time.

In the above figure ,the delta-sigma’s modulator samples and quantize the input signal in a coarse fashion, by producing a one-bit stream of data at a very high rate.
Delta-sigma modulator includes an integrator, which has the effect of shaping the quantization noise.

The Fd value is the corner frequency of the internal digital/decimation filter. One uses Fd to define the corner frequency of delta-sigma converter’s external anti-aliasing filter.

Observe the figure A and figure B above. The modulator sample rate (Fs) shapes the quantization bandwidth. The data rate (Fd) is always smaller than Fs, as in Figure A and B.
Signals in the interval [0, Fd] are included in the converter’s output.
The ENOB describes noise and distortion in the converter’s output data. 

Obviously, ENOB(Fig A) > ENOB(Fig B) .

We have a conclusion that the relationship between the output data rate and the sampling rate directly impacts the effective-number-of-bits (ENOB) at the converter’s output.

1. Modulator provides high-pass filtering property which reduce the noise in low frequency part.

2. Decimation provides that the actual data rate are smaller than sampling frequency which reduce the overall quantization noise. 

The SNR improvement in Delta-Sigma ADC case :
Assume N = delta-sigma modulator order,
For every 2x oversampling rate 
Delta-Sigma ADC get (6xN + 3) dB SNR improvement !

So can we just make N larger (i.e. 3rd order or 4th order delta-sigma modulator) ?

From the figure , it seems fine. But actually while the delta-sigma modulator have order above 2 , there will be some stability problem need to considered.
And if we need large oversampling ratio, it means the clock rate need to be boost up, which in other words the current consumption will be a dominate term of this ADC design.